1. Field of the Invention
The present invention relates to a semiconductor device, particularly one which is comprised of logic circuits and memory circuits.
2. Description of the Related Art
In recent years, attention has been paid to flash memory because it is a nonvolatile semiconductor memory, which is suitable to improve integration (increase capacity). A flash memory cell basically consists of a memory cell with a floating gate. Depending on the accumulation of electric charge in this floating gate, the threshold of the memory cell transistor changes, which means that the information is stored. In this fashion, because the memory cell in flash memory consists of basically only one memory cell transistor, the area occupied by one memory cell is small; thereby improving integration.
However, since flash memory is comprised of only one transistor being used as a memory cell transistor, it is necessary to very precisely adjust the threshold of the memory cell transistor.
Namely, in flash memory, because each memory cell is not fitted with a selection transistor, it is necessary for each memory cell to use its own threshold voltage to decide whether it is selected or not. Due to this, it is not enough for simply each cell to be set to xe2x80x98high thresholdxe2x80x99 or xe2x80x98low thresholdxe2x80x99 dependent upon which information (i.e., either a logical level of xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99) needs to be stored. For example, when storing a certain logical level (writing data) in a memory cell, the threshold voltage of that memory cell transistor is set at or above the gate voltage at the time the memory cell transistor is selected. On the other hand, when storing the other logical level (erasing data) in the memory cell, it is necessary to set the threshold voltage of that memory cell transistor at or below the gate voltage of the memory cell transistor at the time it was selected, but at or above the gate voltage at the time of de-selecting.
For this purpose, when writing data it is unnecessary to accurately adjust the threshold of the memory cell transistor. However, when erasing data it is necessary to very accurately adjust the threshold for it to fall within the above-mentioned range.
Supposing the erase data threshold voltage becomes excessively low, it would go below the de-selected gate voltage. Then regardless of whether it is selected or de-selected, the memory cell transistor would become normally conductive, unable to read-out and it would have what is called xe2x80x98excessive erasurexe2x80x99. Moreover, flash memory has as a feature the one-time block-erasure, but the erasure of the large number of memory cells included in each block is not even; it is dispersed. Because of this, there is much difficulty in getting the erasure threshold voltages of the large number of memory cells erased at one time to fall within the above-mentioned range.
In order to prevent this problem of excessive erasure, various means have been suggested, including the usage of a selective transistor. Using the selective transistor, even when the memory cell transistor is excessively erased, the selective transistor is certain to maintain the non-conductivity of the de-selected memory cell transistor. Accordingly, it is unnecessary for the memory cell transistor threshold voltage to fall within the above-mentioned range at the time of erasure, thereby simplifying the erase function. Meeting the demand for improving the memory access speed, the following type of flash memory has lately attracted attention: the flash memory which uses memory cell transistors and selective transistors, and which is structured as a memory cell array with a primary bit line and secondary bit lines. This type of flash memory makes good use of a technique that controls the possible increase in parasitic capacities caused by the connection of many memory cells to one bit line, and thereby shortening the charging/discharging time of each bit line. To briefly describe this technique any one of m-number of secondary bit lines, each being connected to n-number of memory cells, is selected by m-number of secondary bit line selection transistors, and as a result, is connected to the primary bit line. Consequently, since usually only one secondary bit line is connected to the primary bit line, the parasitic capacities include only the capacities of the primary bit line, the selected, secondary bit line and the n-number of memory cells. Compared to the conventional structure without the primary/secondary bit line arrangement, the total amount of parasitic capacities to be charged and discharged at the time of selection is decreased.
This memory cell array structure, as shown in FIG. 1, is comprised of the following components: the first layer of secondary bit line 103, the second layer of primary bit line 101, a memory cell selective transistor 105 with its source of diffused layer 106, a memory cell 104, and a secondary bit line selective transistor 102. The source of the memory cell 104 is connected to the drain of the memory cell selective transistor 105, whereas the drain of it is connected to the secondary bit line 103. A device separation region 107 separates the secondary bit line selective transistors 102. The source of the transistor 102 is connected to the secondary bit line 103, whereas the drain of it is connected to the primary bit line 101. In this conventional memory cell array structure, the second layer of primary bit lines 101 is made of aluminum wiring, and the first layer of secondary bit line 103 is made of polysilicon wiring.
Since the secondary bit line utilizes polysilicon wiring in the conventional structure, other processes than the one of forming the logic circuit with the metal wiring used for the first layer of wiring so as to facilitate high-speed functioning are needed to form non-volatile memory. This causes an increase in cost when manufacturing a semiconductor device with a hybridized memory/logic circuit. Furthermore, due to the utilization of polysilicon wiring by the secondary bit line, the resistance value of the secondary bit line increases. As a result, the number of memory cells connected to the secondary bit line cannot be increased, nor can the operating speed be increased.
Accordingly, the purpose of this invention is to provide a semiconductor device with hybridized non-volatile memory/logic circuits, which is fabricated in such a manner that the interconnecting process of the non-volatile memory circuit is shared with the logic circuit interconnecting process, and thereby reducing the resistance of the secondary bit lines and also increasing the speed of accessing the non-volatile memory circuit.